TTL gate

Transistor–transistor logic – Wikipedia, the free encyclopedia

The magnitude of this current is about 1.1 mA for a standard TTL gate and does not depend on the number of the parallel connected inputs (base-emitter junctions) belonging to one IC. The input source has to be low-resistive enough (< 800 Ω) so that the flowing current creates only a negligible ...

History - Theory - Packaging - Comparison with other logic ...

en.wikipedia.org/wiki/Transistor–transistor_logic

Logic family - Wikipedia, the free encyclopedia

Since the transistors of a standard TTL gate are saturated switches, minority carrier storage time in each junction limits the switching speed of the device. Variations on the basic TTL design are intended to reduce these effects and improve speed, power consumption, or both. The German ...

en.wikipedia.org/wiki/Logic_family

TTL logic gates This worksheet and all related files are licensed ...

For a true TTL gate (not high-speed CMOS), what is the default logic state of an input line that is left. floating (neither connected to VCC nor Ground)? Explain ...

What is the typical range of supply voltages for a true TTL gate, and why can't this type. of logic gate operate from a wider range of voltages as ...

IOL is typically much greater than IOH for a TTL gate with totem-pole output circuitry. The reason. for this should be obvious from inspection of ...

http://www.ibiblio.org/kuphaldt/socratic/output/ttl.pdf

Suppose we altered our basic open-collector inverter circuit, adding a second input terminal just like the first:

This schematic illustrates a real circuit, but it isn’t called a “two-input inverter.” Through analysis we will discover what this circuit’s logic function is and correspondingly what it should be designated as.

Just as in the case of the inverter and buffer, the “steering” diode cluster marked “Q₁” is actually formed like a transistor, even though it isn’t used in any amplifying capacity. Unfortunately, a simple NPN transistor structure is inadequate to simulate the three PN junctions necessary in this diode network, so a different transistor (and symbol) is needed. This transistor has one collector, one base, and twoemitters, and in the circuit it looks like this:

In the single-input (inverter) circuit, grounding the input resulted in an output that assumed the “high” (1) state. In the case of the open-collector output configuration, this “high” state was simply “floating.” Allowing the input to float (or be connected to V_cc) resulted in the output becoming grounded, which is the “low” or 0 state. Thus, a 1 in resulted in a 0 out, and vice versa.

Since this circuit bears so much resemblance to the simple inverter circuit, the only difference being a second input terminal connected in the same way to the base of transistor Q₂, we can say that each of the inputs will have the same effect on the output. Namely, if either of the inputs are grounded, transistor Q₂ will be forced into a condition of cutoff, thus turning Q₃ off and floating the output (output goes “high”). The following series of illustrations shows this for three input states (00, 01, and 10):

In any case where there is a grounded (“low”) input, the output is guaranteed to be floating (“high”). Conversely, the only time the output will ever go “low” is if transistor Q₃ turns on, which means transistor Q₂ must be turned on (saturated), which means neither input can be diverting R₁ current away from the base of Q₂. The only condition that will satisfy this requirement is when both inputs are “high” (1):

Collecting and tabulating these results into a truth table, we see that the pattern matches that of the NAND gate:

In the earlier section on NAND gates, this type of gate was created by taking an AND gate and increasing its complexity by adding an inverter (NOT gate) to the output. However, when we examine this circuit, we see that the NAND function is actually the simplest, most natural mode of operation for this TTL design. To create an AND function using TTL circuitry, we need to increase the complexity of this circuit by adding an inverter stage to the output, just like we had to add an additional transistor stage to the TTL inverter circuit to turn it into a buffer:

The truth table and equivalent gate circuit (an inverted-output NAND gate) are shown here:

Of course, both NAND and AND gate circuits may be designed with totem-pole output stages rather than open-collector. I am opting to show the open-collector versions for the sake of simplicity.

REVIEW:
A TTL NAND gate can be made by taking a TTL inverter circuit and adding another input.
An AND gate my be created by adding an inverter stage to the output of the NAND gate circuit.

TTL NOR and OR gates

Let’s examine the following TTL circuit and analyze its operation:

Transistors Q₁ and Q₂ are both arranged in the same manner that we’ve seen for transistor Q₁ in all the other TTL circuits. Rather than functioning as amplifiers, Q₁ and Q₂ are both being used as two-diode “steering” networks. We may replace Q₁ and Q₂ with diode sets to help illustrate:

If input A is left floating (or connected to V_cc), current will go through the base of transistor Q₃, saturating it. If input A is grounded, that current is diverted away from Q₃‘s base through the left steering diode of “Q₁,” thus forcing Q₃ into cutoff. The same can be said for input B and transistor Q₄: the logic level of input B determines Q₄‘s conduction: either saturated or cutoff.

Notice how transistors Q₃ and Q₄ are paralleled at their collector and emitter terminals. In essence, these two transistors are acting as paralleled switches, allowing current through resistors R₃ and R₄ according to the logic levels of inputs A and B. If any input is at a “high” (1) level, then at least one of the two transistors (Q₃ and/or Q₄) will be saturated, allowing current through resistors R₃ and R₄, and turning on the final output transistor Q₅ for a “low” (0) logic level output. The only way the output of this circuit can ever assume a “high” (1) state is if both Q₃ and Q₄ are cutoff, which means both inputs would have to be grounded, or “low” (0).

This circuit’s truth table, then, is equivalent to that of the NOR gate:

In order to turn this NOR gate circuit into an OR gate, we would have to invert the output logic level with another transistor stage, just like we did with the NAND-to-AND gate example: